Apparatus for limiting instantaneous inverter current

ABSTRACT

The invention relates to a technique for limiting the peak transient currents in the power switches of an inverter wherein a current control circuit compares the current flow in the power switches of the inverter to a reference value and provides protective ON-OFF control of the power switches to prevent overload of the power switches. In the event the current flow through a power switch exceeds a predetermined value, the current control circuit overrides the main power switch ON-OFF control circuit and generates an inhibit signal which turns the power switch off for a period of time required to allow the current magnitude to decrease a predetermined amount at which time the current control circuit inhibit signal is removed and the main power switch ON-OFF control circuit resumes control of the power switch conduction.

United States Patent [191 Kernick et al.

[ May 15, 1973 FOREIGN PATENTS OR APPLICATIONS 4/1969 Great Britain..321/l4 Primary ExaminerGerald Goldberg Attorney-F. H. Henson, CharlesF. Renz and Michael P. Lynch ABSTRACT The invention relates to atechnique for limiting the peak transient currents in the power switchesof an inverter wherein a current control circuit compares the currentflow in the power switches of the inverter to a reference value andprovides protective ON-OFF control of the power switches to preventoverload of the power switches. In the event the current flow through apower switch exceeds a predetermined value, the current control circuitoverrides the main power switch ON-OFF control circuit and generates aninhibit signal which turns the power switch off for a period of timerequired to allow the current magnitude to decrease a predeterminedamount at which time the current control circuit inhibit signal isremoved and the main power switch ON-OFF control circuit resumes controlof the power switch conduc- 4 Claims, 5 Drawing Figures [54] APPARATUSFOR LIMITING INSTANTANEOUS INVERTER l 148 680 CURRENT [75] Inventors:Andress Kernick, Lima; Glenn W. Ernsberger, Worthington, both of Ohio[73] Assignee: Westinghouse Electric Corporation,-

Pittsburgh, Pa. [57] [22] Filed: Aug. 17, 1970 [21] Appl. No.: 64,442

[52] US. Cl ..32l/13, 317/33 R, 321/14, 323/9 [51] Int. Cl. ..H02m 1/18,H02h 7/10 [58] Field of Search ..321/l1,i3,14; 317/20, 30, 33, 22, 50;323/9 7 [56] References Cited UNITED STATES PATENTS 3,444,453 5/1969Peterson ..321/l1 3,320,514 5/1967 Lawrence ..321/l3 3,490,027 l/l970Galetto et al ..321/ll X 3,551,748 12/1970 Maynard et al ..321/11 X iANDRE'CHOKE 0.0. g SOURCE MAlN CONTROL SOURCE PAIEI-ITEU HAY I 51975 D.CSOURCE SHEET 1 OF 2 MAIN CONTROL CIRCUIT VOLTAGE SOURCE MAIN CONTROLSOURCE PATENTEU W I W SHEET 2 BF 2 TIME ' REF CURRENT CONTROL DEAD BANDI I 50/o V Ill L FIG?) MAx VOLTAGE SOURCE FIG.4

VOLTAGE SOURCE APPARATUS FOR LIMITING INSTANTANEOUS INVERTER CURRENT iBACKGROUND OF THE INVENTION In many power inverter circuits, currentlimitingis accomplished by sensing the power inverter output current, orload current, with a current transformer, rectifying and filtering thevoltage developed across a burden resistor and comparing this voltagewith a DC voltage reference in a voltage regulator circuit. While thisprior art technique provides good steady state current limiting, it isgenerally insensitive to peak currents produced during short-circuitconditions as well as transient currents resulting from saturation ofthe inverter output transformer.

SUMMARY OF THE INVENTION The invention overcomes the limitations of theprior art current limiting techniques by sensing the instantaneous valueof the current flow through the power switches comprising the inverterrather than sensing the output load current of the inverter.

A current transformer is connected in the inverter circuit such that thecurrent flow through the power switches passes through the primarywinding of the current transformer. The current appearing across thesecondary winding of the transformer is converted into a representativevoltage signal and compared to a DC reference voltage input of a currentcontrol circuit. When the voltage signal corresponding to the currentflow through the power switches exceeds the DC reference voltage, thecurrent control circuit generates an inhibit signal which turns thepower switches OFF and reduces the magnitude of the DC reference voltagea predetermined amount, i.e., 50-75 percent. Due to circuit and loadinductances, the load current takes a tinite period of time to decrease50 to 75 percent. When the magnitude of the voltage signal correspondingto the current flow through the power switches decreases below thereduced DC reference voltage, the current control circuit removes theinhibit signal and restores the DC reference voltage to its originalmagnitude.

The invention will become more readily apparent from the followingexemplary description in connection with the accompanying drawing.

DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERRED EMBODIMENTReferring to FIG. 1, there is illustrated schematically a typical powerinverter circuit including a bridge type power stage 12 comprisingtransistor power switches 13, an output transformer 14 connected acrossa load 15, and a main control circuit 16 for controlling the conductionof the power switches 13 to develop the desired power inverter outputvoltage. While the power switches 13 are represented to be transistors,it is understood that other switching devices such as the SCR (siliconcontrolled rectifier) and the GCS (gate controlled switch) are equallysuitable in this application. A current control circuit 20 is coupled tothe power inverter circuit 10 by a current transformer CT and respondsto transient current flow through the transistors 13 by generating aninhibit signal L and M to override the operation of the main controlcircuit 16 until the transient condition is brought under control.Numerous methods are available for implementing the sequential gating orfiring function of the main control circuit 16. One such method isdisclosed in the copending application Ser. No. 14,314, filed Feb. 26,1970 and entitled Apparatus For Producing A Low Distortion Pulse WidthModulated Inverter Output.

The current transformer primary winding CTP is connected in series withthe output transformer 14 of the power inverter circuit 10 so that thecurrent flow through the transistor power switches 13 passes through theprimary winding CTP. In the event a center-tapped parallel power stageis used instead of the bridge type illustrated, two primary windingsCTPl and CTP2 would be utilized, as illustrated in FIG. 2.

A single current transformer core is sufficient in the absence of a dccurrent component in the ac transient currents being monitored by thecurrent control circuit 20. However unbalance in half cycle currentswhich results in a dc current component is often encountered as a resultof saturation of the inverter output transformer. In order to preventsaturation of the current transformer CT, dual transformer cores Cl andC2 are used. The dual cores operate in an alternate manner inconjunction with the input circuit 21 of the current control circuit 20.The input circuit comprises resistor combinations Rl-Rl' and R2-R2' andassociated diodes CR1 and CR2. While one core is developing an inputsignal across one resistor combination associated with a forward biaseddiode, the other core is resetting into a relatively high burdenresistance resulting from the reverse bias condition of its associateddiode. The capability of completely resetting the cores Cl and C2 duringalternate half cycles, enables each core to deliver maximum volt-secondsduring the respective active half cycle corresponding to the dotpositive winding designations. In the absence of the dc currentcomponent, the dual cores C1 and C2 may be replaced with a single coreand the burden resistors R1 and R2 eliminated.

The current control circuit 20 includes two comparator circuits CA andCB which function to generate the inhibit signals L and M respectivelydepending upon the polarity condition of the inverter power stage 12 atthe instant of transistor overload.

The polarity sensitivity of the comparator circuits CA and CB isprovided by the center-tapped secondary winding CTS of the currenttransformer CT. The current flow through transistors 13A during thepositive half-cycle of the inverter output current is monitored by thecircuitry associated with comparator circuit CA, and the current flowthrough transistors 13B during the negative half-cycle is monitored bythe circuitry associated with the comparator circuit CB. The inputcircuit 21 which is connected across the center-tapped secondary windingCTS responds to the current flow through the diode rectifiers CR1 andCR2 by developing a voltage signal representative of transistor currentflow corresponding to the positive and negative current polarity of theinverter power stage 12. The voltage signals developed across theresistor combinations RlRl and R2-R2' are supplied to the negativeinputs CAN and CBN of the comparator circuits CA and CB respectively.The output of a DC voltage source S is applied to a resistor voltagedivider circuit comprised of resistors R3 and R4 which develops a DCreference voltage V which is supplied to the positive input CAP and CBPof the comparator circuits CA and CB respectively. The comparatorcircuits CA and CB, which are illustrated in FIG. 1 as integratedcircuit type comparator circuits, generate output signals of a polaritycorresponding to the polarity of the larger input signal and of amagnitude sufficient to override the transistor conduction control ofthe main control circuit 16.

Under normal inverter output conditions the magnitude of the voltagesignal developed across resistors Rl-Rl and R2R2 in response to thepositive and negative polarity swings of the inverter output current isless than the magnitude of the reference voltage V The output of thecomparator circuits CA and CB is therefore positive which results in theturning OFF of transistors Q1 and Q2 and the absence of inhibit signalsL and M. In the absence of inhibit signals L and M the transistors 13Aand 13B of the bridge type power stage 12 are permitted to conduct inaccordance with the firing sequence established by the main controlcircuit 16.

In the event the magnitude of the voltage developed across resistorcombination Rl-Rl exceeds the magnitude of the reference voltage V as aresult of an overload current flow through the transistors 13A, theoutput of the comparator circuit CA will be negative. This negativeoutput voltage condition results in the forward biasing of diode CR3 andthe turning ON of transistor Q1 which results in the generation of aninhibit signal L. The forward biasing of diode CR3 provides a currentflow through resistor R7 which functions to decrease the magnitude ofthe reference voltage V supplied to the positive input of the comparatorcircuits CA and CB. The combination of the resistor R7 and the diode CR3forms a hysteresis type circuit. The attenuating effect of resistor R7can be varied to provide a suitable current control deadband withinwhich the inhibit signal A turns OFF the transistors 13A until theinverter output current as represented by the voltage developed acrossresistor combination Rl-Rl' drops below a predetermined value, i.e., avalue corresponding to 50 percent of the maximum allowable inverteroutput current. An inverter output current depicting the transistoroverload current control provided by circuit is illustrated in FIG. 3.

Due to circuit and load inductances the current flow does not cease withturn-off of the transistors 13A, rather the primary winding CTP issubjected to a reverse current flow through a path provided by thecommutating diodes 17 associated with transistors 138. This reversecurrent flow through the diodes 17 appears the same as the forwardcurrent flow through the transistors 13A to the current transformer CT.The decaying current resulting from the generation of the inhibit signalflows through the primary winding CTP via a path provided by thecommutating diodes associated with the opposite leg of the invertercircuit. When the voltage across the resistor combination Rl-Rl' dropsbelow the reduced reference voltage 50 percent V the output of thecomparator circuit CA again becomes positive thereby returningtransistor O1 to the OFF state and returning the magnitude of thereference to its original value V This cyclic current control providedby circuit 20 may be repeated many times during a half-cycle of theinverter output current as evidenced by the waveform of FIG. 3.

During the negative half-cycle of the output current, the current flowin the secondary winding CTS ofa current transformer CT flows throughdiode CR2 and develops a voltage across the resistor combination R2-R2.Excessive inverter output current flow represented by a voltage acrossresistors R2-R2 which exceeds the magnitude of the reference voltage Vestablishes a negative output from comparator circuit CB which turnstransistor Q2 ON and forward biases diode CR4. The inhibit signal Mproduced by the ON condition of the transistor Q2 turns transistors 13BOFF until the voltage across resistors R2R2 drops below the reducedreference voltage 50 percent V established by the current flow throughresistor R7 and diode CR4.

Referring to FIG. 4 there is illustrated a modification of the currentcontrol circuit 20 which provides separate hysteresis circuits for eachcomparator circuit through the addition of resistors R7, R8, R9, R10 andfilter capacitor C1.

FIG. 5 illustrates a variation of the current control circuit 20 of FIG.1 in which the integrated circuit comparators are replaced with discretecomponent circuits. At the present time this approach represents theleast expensive method of providing the control required. A DC referencevoltage is established at the emitter of transistors Q10 and Q12 byresistors R13 and R14. Assuming that an overload exists and the voltageacross R10 causes Q10 to conduct through resistor R15 and the base oftransistor Q13. This causes transistor Q13 to conduct current to theoutput L and also through resistor R20 into the base of the transistorQ15. When the transistor Q15 conducts current through the resistors R17and R13, it lowers the reference voltage level at the emitters of thetransistors Q10 and Q12 and provides the desired control currentdeadband or hysteresis. When the inverter output current magnitudedecreases and the voltage developed across the resistor R10 can nolonger maintain the transistor Q10 in a state of conduction, thetransistors Q10, Q13 and Q15 turn OFF. When inverter output overloadcurrent occurs with the opposite polarity, transistors O12, Q14 and Q15conduct in a similar manner.

Experimental use of the current control circuits thus described havedemonstrated instantaneous protection of inverter power thyristors fromsudden applications of overload or short-circuit currents. Through theoperation of the current control circuit the output inverter currentapproaches a square-wave G as shown in FIG. 3 when a short-circuit isapplied to the inverter. This waveform provides a maximum possible RMSoutput current for a given peak switching current capability.

We claim:

1. In a dc to ac electrical inverter circuit including first and secondON-OFF conduction control power switch means for developing an ac loadcurrent, the combination of, a first circuit means for providingalternate ON-OFF conduction control of said first and second conductioncontrol power switch means, second circuit means operatively connectedto said inverter circuit for monitoring the current flow through each ofsaid first and second conduction control power switching means while inan ON state established by said first circuit means and developing anoutput signal representative of the magnitude of said current, saidsecond circuit means including a current transformer means having aprimary winding operatively connected in said inverter circuit, saidcurrent flow through said first and second conduction control switchmeans passing through said primary winding, and a secondary winding,third circuit means for generating a reference signal, a fourth circuitmeans operatively connected to said secondary winding for developingsaid output signal in the form of a first voltage signal correspondingto the current flow through said first conduction controlled powerswitch means and a second voltage signal corresponding to the currentflow through said second conduction controlled power switch means, and acurrent control circuit means operatively connected to said fourthcircuit means for comparing said output signals of said fourth circuitmeans with said reference signal and generating an inhibit signal when apredetermined relationship exists between the magnitude of said outputsignals and the magnitude of said reference signal indicative of theexcessive current flow through the ON power switch means, said inhibitsignal being applied to said first circuit means to override the ON- OFFconduction control of the ON power switch means and turning said ONpower switch means OFF until the magnitude of said current decreases toa predetermined value at which time said first circuit means resumesON-OFF conduction control.

2. In a dc to ac electrical inverter circuit as claimed in claim 1wherein said third circuit includes a dc voltage source and saidreference signal is a dc voltage signal, and said current control meansincludes a first and second comparator means, each having first andsecond inputs, and an output, said reference signal being supplied tosaid first inputs of said first and second comparator circuit means,said first voltage signal of said fourth circuit means being supplied tothe second input of said first comparator circuit means and said secondvoltage signal of said fourth circuit means being supplied to the secondinputof said second comparator circuit means, a first inhibit signalgenerating circuit operatively connected to said output of firstcomparator circuit means, and a second inhibit signal generating circuitoperatively connected to said output of said second comparator circuitmeans, said first and second inhibit signal generating circuits beingactivated to generate inhibit signals in response to outputs of saidfirst and second comparator circuit means corresponding to inputconditions in which the magnitude of the voltage signals supplied tosaid second inputs exceeds the magnitude of the reference voltage signalsupplied to said first inputs.

3. In a dc to ac electrical inverter circuit as claimed in claim 1including a fifth circuit means for reducing the magnitude of saidreference signal by a predetermined amount in response to the generatingof said inhibit signal, the magnitude of said reference signal beingrestored to its initial value when said inhibit signal is terminated.

4. In a dc to ac electrical inverter circuit as claimed in claim 1wherein said current transformer includes a first and second primarywinding and a first and second core for coupling said first and secondprimary windings to said center tap secondary windings, said first andsecond voltage signals developed by said fourth circuit meanscorresponding to the current flow through the first and second primarywindings respectively, said fourth circuit means including impedancecircuit means for alternately resetting the individual primary windingduring the inactive half cycles of their respec- .tive conductioncontrolled power switch means.

1. In a dc to ac electrical inverter circuit including first and secondON-OFF conduction control power switch means for developing an ac loadcurrent, the combination of, a first circuit means for providingalternate ON-OFF conduction control of said first and second conductioncontrol power switch means, second circuit means operatively connectedto said inverter circuit for monitoring the current flow through each ofsaid first and second conduction control power switching means while inan ON state established by said first circuit means and developing anoutput signal representative of the magnitude of said current, saidsecond circuit means including a current transformer means having aprimary winding operatively connected in said inverter circuit, saidcurrent flow through said first and second conduction control switchmeans passing through said primary winding, and a secondary Winding,third circuit means for generating a reference signal, a fourth circuitmeans operatively connected to said secondary winding for developingsaid output signal in the form of a first voltage signal correspondingto the current flow through said first conduction controlled powerswitch means and a second voltage signal corresponding to the currentflow through said second conduction controlled power switch means, and acurrent control circuit means operatively connected to said fourthcircuit means for comparing said output signals of said fourth circuitmeans with said reference signal and generating an inhibit signal when apredetermined relationship exists between the magnitude of said outputsignals and the magnitude of said reference signal indicative of theexcessive current flow through the ON power switch means, said inhibitsignal being applied to said first circuit means to override the ON-OFFconduction control of the ON power switch means and turning said ONpower switch means OFF until the magnitude of said current decreases toa predetermined value at which time said first circuit means resumesON-OFF conduction control.
 2. In a dc to ac electrical inverter circuitas claimed in claim 1 wherein said third circuit includes a dc voltagesource and said reference signal is a dc voltage signal, and saidcurrent control means includes a first and second comparator means, eachhaving first and second inputs, and an output, said reference signalbeing supplied to said first inputs of said first and second comparatorcircuit means, said first voltage signal of said fourth circuit meansbeing supplied to the second input of said first comparator circuitmeans and said second voltage signal of said fourth circuit means beingsupplied to the second input of said second comparator circuit means, afirst inhibit signal generating circuit operatively connected to saidoutput of first comparator circuit means, and a second inhibit signalgenerating circuit operatively connected to said output of said secondcomparator circuit means, said first and second inhibit signalgenerating circuits being activated to generate inhibit signals inresponse to outputs of said first and second comparator circuit meanscorresponding to input conditions in which the magnitude of the voltagesignals supplied to said second inputs exceeds the magnitude of thereference voltage signal supplied to said first inputs.
 3. In a dc to acelectrical inverter circuit as claimed in claim 1 including a fifthcircuit means for reducing the magnitude of said reference signal by apredetermined amount in response to the generating of said inhibitsignal, the magnitude of said reference signal being restored to itsinitial value when said inhibit signal is terminated.
 4. In a dc to acelectrical inverter circuit as claimed in claim 1 wherein said currenttransformer includes a first and second primary winding and a first andsecond core for coupling said first and second primary windings to saidcenter tap secondary windings, said first and second voltage signalsdeveloped by said fourth circuit means corresponding to the current flowthrough the first and second primary windings respectively, said fourthcircuit means including impedance circuit means for alternatelyresetting the individual primary winding during the inactive half cyclesof their respective conduction controlled power switch means.